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MPC7441EC/D Rev. 0, 10/2001 MPC7441 RISC Microprocessor Hardware Specifications
The MPC7441 is a reduced instruction set computing (RISC) microprocessor that implements the PowerPC instruction set architecture. This document describes pertinent electrical and physical characteristics of the MPC7441. For functional characteristics of the processor, refer to the MPC7450 RISC Microprocessor Family User's Manual. This document contains the following topics:
Topic Page
Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "Comparison with the MPC7400" Section 1.4, "General Parameters" Section 1.5, "Electrical and Thermal Characteristics" Section 1.6, "Pin Assignments" Section 1.7, "Pinout Listings for the 360 CBGA Package" Section 1.8, "Package Description" Section 1.9, "System Design Information" Section 1.10, "Document Revision History" Section 1.11, "Ordering Information" To locate any published updates for this document, refer to the website at http://www.motorola.com/semiconductors
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1.1
Overview
The MPC7441 is the third implementation of the fourth generation (G4) microprocessors from Motorola. The MPC7441 implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The MPC7441 consists of a processor core and a 256-Kbyte L2. Figure 1 shows a block diagram of the MPC7441. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus interface to main memory and other system resources.
PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
Overview
2 MPC7441 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Figure 1. MPC7441 Block Diagram
Additional Features * Time Base Counter/Decrementer * Clock Multiplier * JTAG/COP Interface * Thermal/Power Management * Performance Monitor
96-Bit (3 Instructions)
Instruction Unit Branch Processing Unit BTIC (128-Entry) BHT (2048-Entry) CTR Fetcher
Instruction Queue (12-Word)
Instruction MMU SRs (Shadow) 128-Entry ITLB
128-Bit (4 Instructions)
Tags
IBAT Array LR Dispatch Unit Data MMU SRs (Original) VR Issue (4-Entry/2-Issue) GPR Issue (6-Entry/3-Issue) FPR Issue (2-Entry/1-Issue) 128-Entry DTLB Tags
32-Kbyte I Cache
32-Kbyte D Cache
DBAT Array
Reservation Stations (2-Entry) Vector Touch Queue GPR File 16 Rename Buffers
EA
Load/Store Unit Vector Touch Engine + (EA Calculation) Finished Stores L1 Castout PA FPR File 16 Rename Buffers Reservation Stations (2)
Reservation Reservation Reservation Reservation Station Station Station Station
VR File 16 Rename Buffers
Reservation Stations (2)
Reservation Reservation Reservation Station Station Station
Vector Permute Unit
Vector Integer Unit 2
Vector Integer Unit 1
Vector FPU
Integer Unit 2 x/
Integer Integer Integer Unit 122 Unit Unit (3) +++
FloatingPoint Unit + x/ FPSCR
L1 Push Completed Stores
32-Bit 128-Bit 128-Bit
32-Bit
32-Bit
Load Miss
64-Bit
64-Bit
Completion Unit Completion Queue (16-Entry) Memory Subsystem System Bus Interface L2 Prefetch (3) Bus Store Queue Push Castout Queue (9) L2 Store Queue (L2SQ) Snoop Push/ Interventions 256-Kbyte Unified L2 Cache/Cache Controller Line Block 0 (32-Byte) Block 1 (32-Byte) Tags Status Status L1 Service Queues L1 Store Queue (LSQ) L1 Load Queue (LLQ) L1 Load Miss (5) Instruction Fetch (2) Cacheable Store Request (1)
L1 Castouts (4)
Bus Accumulator Completes up to three instructions per clock 36-Bit Address Bus 64-Bit Data Bus
Features
1.2
Features
This section summarizes features of the MPC7441 implementation of the PowerPC architecture. Major features of the MPC7441 are as follows: Major features of the MPC7441 are as follows: * High-performance, superscalar microprocessor -- As many as 4 instructions can be fetched from the instruction cache at a time -- As many as 3 instructions can be dispatched to the issue queues at a time -- As many as 12 instructions can be in the instruction queue (IQ) -- As many as 16 instructions can be at some stage of execution simultaneously -- Single-cycle execution for most instructions -- One instruction per clock cycle throughput for most instructions -- Seven-stage pipeline control * Eleven independent execution units and three register files -- Branch processing unit (BPU) features static and dynamic branch prediction - 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache of branch instructions that have been encountered in branch/loop code sequences. If a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. Typically, a fetch that hits the BTIC provides the first four instructions in the target stream. - 2048-entry branch history table (BHT) with two bits per entry for four levels of prediction-- not-taken, strongly not-taken, taken, strongly taken - Up to three outstanding speculative branches - Branch instructions that do not update the count register (CTR) or link register (LR) are often removed from the instruction stream. - 8-entry link register stack to predict the target address of Branch Conditional to Link Register (bclr) instructions. -- Four integer units (IUs) that share 32 GPRs for integer operands - Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions. - IU2 executes miscellaneous instructions including the CR logical operations, integer multiplication and division instructions, and move to/from special-purpose register instructions. -- Five-stage FPU and a 32-entry FPR file - Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations - Supports non-IEEE mode for time-critical operations - Hardware support for denormalized numbers - Thirty-two 64-bit FPRs for single- or double-precision operands -- Four vector units and 32-entry vector register file (VRs) - Vector permute unit (VPU)
MOTOROLA
MPC7441 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Features
- Vector integer unit 1 (VIU1) handles short-latency AltiVec integer instructions, such as vector add instructions (vaddsbs, vaddshs, and vaddsws, for example) - Vector integer unit 2 (VIU2) handles longer -latency AltiVec integer instructions, such as vector multiply add instructions (vmhaddshs, vmhraddshs, and vmladduhm, for example). - Vector floating-point unit (VFPU) -- Three-stage load/store unit (LSU) - Supports integer, floating-point and vector instruction load/store traffic - Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream operations - Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with 1-cycle throughput - Four-cycle FPR load latency (single, double) with 1-cycle throughput - No additional delay for misaligned access within double-word boundary - Dedicated adder calculates effective addresses (EAs) - Supports store gathering - Performs alignment, normalization, and precision conversion for floating-point data - Executes cache control and TLB instructions - Performs alignment, zero padding, and sign extension for integer data - Supports hits under misses (multiple outstanding misses) - Supports both big- and little-endian modes, including misaligned little-endian accesses * Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions, respectively, in a cycle. Instruction dispatch requires the following: -- Instructions can be dispatched only from the three lowest IQ entries--IQ0, IQ1, and IQ2. -- A maximum of three instructions can be dispatched to the issue queues per clock cycle. -- Space must be available in the CQ for an instruction to dispatch (this includes instructions that are assigned a space in the CQ but not in an issue queue). * Rename buffers -- 16 GPR rename buffers -- 16 FPR rename buffers -- 16 VR rename buffers * * Dispatch unit -- The decode/dispatch stage fully decodes each instruction. Completion unit -- The completion unit retires an instruction from the 16-entry completion queue (CQ) when all instructions ahead of it have been completed, the instruction has finished execution, and no exceptions are pending. -- Guarantees sequential programming model (precise exception model) -- Monitors all dispatched instructions and retires them in order
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Features
-- Tracks unresolved branches and flushes instructions after a mispredicted branch -- Retires as many as three instructions per clock cycle * Separate on-chip L1 instruction and data caches (Harvard architecture) -- 32-Kbyte, eight-way set-associative instruction and data caches -- Pseudo least-recently-used (PLRU) replacement algorithm -- 32-byte (eight-word) L1 cache block -- Physically indexed/physical tags -- Cache write-back or write-through operation programmable on a per-page or per-block basis -- Instruction cache can provide four instructions per clock cycle; data cache can provide four words per clock cycle -- Caches can be disabled in software -- Caches can be locked in software -- MESI data cache coherency maintained in hardware -- Separate copy of data cache tags for efficient snooping -- Parity support on cache and tags -- No snooping of instruction cache except for icbi instruction -- Data cache supports AltiVec LRU and transient instructions -- Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical double-word forwarding. * Level 2 (L2) cache interface -- On-chip, 256-Kbyte, 8-way set associative unified instruction and data cache -- Fully pipelined to provide 32 bytes per clock cycle to the L1 caches -- A total 9-cycle load latency for an L1 data cache miss that hits in L2 -- Pseudo least-recently-used (PLRU) replacement algorithm -- Cache write-back or write-through operation programmable on a per-page or per-block basis -- 64-byte, two-sectored line size -- Parity support on cache * Separate memory management units (MMUs) for instructions and data -- 52-bit virtual address; 32- or 36-bit physical address -- Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments -- Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and memory coherency enforced/memory coherency not enforced on a page or block basis -- Separate IBATs and DBATs (four each) also defined as SPRs -- Separate instruction and data translation lookaside buffers (TLBs) - Both TLBs are 128-entry, two-way set associative, and use LRU replacement algorithm - TLBs are hardware- or software-reloadable (that is, on a TLB miss a page table search is performed in hardware or by system software)
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Features
*
Efficient data flow -- Although the VR/LSU interface is 128 bits, the L1/L2 bus interface allows up to 256 bits. -- The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs -- L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache. -- As many as 8 outstanding, out-of-order, cache misses are allowed between the L1 data cache and L2 bus. -- As many as 16 out-of-order transactions can be present on the MPX bus -- Store merging for multiple store misses to the same line. Only coherency action taken (address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed). -- Three-entry finished store queue and five-entry completed store queue between the LSU and the L1 data cache -- Separate additional queues for efficient buffering of outbound data (such as cast outs and write through stores) from the L1 data cache and L2 cache
*
Multiprocessing support features include the following: -- Hardware-enforced, MESI cache coherency protocols for data cache -- Load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations
*
Power and thermal management -- 1.5-V processor core -- The following three power-saving modes are available to the system: - Nap--Instruction fetching is halted. Only those clocks for the thermal assist unit (TAU), time base, decrementer, and JTAG logic remain running. The part goes into the doze state to snoop memory operations on the bus and then back to nap using a QREQ/QACK processor-system handshake protocol. - Sleep--Power consumption is further reduced by disabling bus snooping, leaving only the PLL in a locked and running state. All internal functional units are disabled. - Deep sleep--When the part is in the sleep state, the system can disable the PLL resulting. The system can then disable the SYSCLK source for greater system power savings. Power-on reset procedures for restarting and relocking the PLL must be followed on exiting the deep sleep state. -- Thermal management facility provides software-controllable thermal management. Thermal management is performed through the use of three supervisor-level registers and an MPC7441-specific thermal management exception. -- Instruction cache throttling provides control of instruction fetching to limit power consumption.
* * *
Performance monitor can be used to help debug system designs and improve software efficiency. In-system testability and debugging features through JTAG boundary-scan capability Testability -- LSSD scan design -- IEEE 1149.1 JTAG interface -- Array built-in self test (ABIST)--factory test only
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Comparison with the MPC7400
*
Reliability and serviceability -- Parity checking on system bus -- Parity checking on L1 and L2
1.3
Comparison with the MPC7400
Table 1 compares the key features of the MPC7441 with the key features of the earlier MPC7400. To achieve a higher frequency, the number of logic levels per cycle is reduced. Also, to achieve this higher frequency, the pipeline of the MPC7441 is extended (compared to the MPC7400), while maintaining the same level of performance as measured by the number of instructions executed per cycle (IPC).
Table 1. Microarchitecture Comparison
Microarchitectural Specs MPC7441 Basic Pipeline Functions Logic Inversions per Cycle Pipeline Stages up to Execute Total Pipeline Stages (Minimum) Pipeline Maximum Instruction Throughput Pipeline Resources Instruction Buffer Size Completion Buffer Size Renames (Integer, Float, Vector) 12 16 16, 16, 16 Maximum Execution Throughput SFX Vector Scalar Floating-Point 3 2 (Any 2 of 4 Units) 1 Out-of-Order Window Size in Execution Queues SFX Integer Units Vector Units Scalar Floating-Point Unit 1 Entry x 3 Queues In Order, 4 Queues In Order Branch Processing Resources Prediction Structures BTIC Size, Associativity BHT Size Link Stack Depth Unresolved Branches Supported Branch Taken Penalty (BTIC Hit) Minimum Misprediction Penalty BTIC, BHT, Link Stack 128-Entry, 4-Way 2K-Entry 8 3 1 6 BTIC, BHT 64-Entry, 4-Way 512-Entry None 2 0 4 1 Entry x 2 Queues In Order, 2 Queues In Order 2 2 (Permute/Fixed) 1 6 8 6, 6, 6 18 5 7 3 + Branch 28 3 4 2 + Branch MPC7400/MPC7410
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Comparison with the MPC7400 Table 1. Microarchitecture Comparison (continued)
Microarchitectural Specs MPC7441 MPC7400/MPC7410
Execution Unit Timings (Latency-Throughput) Aligned Load (Integer, Float, Vector) Misaligned Load (Integer, Float, Vector) L1 Miss, L2 Hit Latency SFX (aDd Sub, Shift, Rot, Cmp, Logicals) Integer Multiply (32 x 8, 32 x 16, 32 x 32) Scalar Float VSFX (Vector Simple) VCFX (Vector Complex) VFPU (Vector Float) VPER (Vector Permute) MMUs MMUs (Instruction and Data) Tablewalk Mechanism 128-Entry, 2-Way Hardware + Software L1 I Cache/D Cache Features Size Associativity Locking Granularity/Style Parity on I Cache Parity on D Cache Number of D Cache Misses (Load/Store) Data Stream Touch Engines 32K/32K 8-Way 4-Kbyte/Way Word Byte 5/1 4 Streams On-Chip Cache Features Cache Level Size/Associativity Access Width Number of 32-Byte Sectors/Line Parity Off-Chip Cache Support Cache Level On-Chip Tag Logical Size Associativity Number of 32-Byte Sectors/Line Off-Chip Data SRAM Support Data Path Width N/A N/A N/A N/A N/A N/A L2 0.5MB, 1MB, 2MB 2-Way 1, 2, 4 LW, PB2, PB3 64 L2 256-Kbyte/8-Way 256 Bits 2 Byte None (Except L1) N/A N/A N/A N/A 32K/32K 8-Way Full Cache None None 8 (Any Combination) 4 Streams 128-Entry, 2-Way Hardware 3-1, 4-1, 3-1 4-2, 5-2, 4-2 6 (9) 1-1 3-1, 3-1, 4-2 5-1 1-1 4-1 4-1 2-1 2-1, 2-1, 2-1 3-2, 3-2, 3-2 9 (11)1 1-1 2-1, 3-2, 5-4 3-1 1-1 3-1 4-1 1-1
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General Parameters Table 1. Microarchitecture Comparison (continued)
Microarchitectural Specs Direct Mapped SRAM Sizes Parity
1
MPC7441 N/A N/A
MPC7400/MPC7410 0.5 Mbyte, 1 Mbyte, 2 Mbytes Byte
Numbers in parentheses are for 2:1 SRAM.
1.4
Die size
General Parameters
0.18 m CMOS, six-layer metal 8.69 mm x 12.17 mm (106 mm2) 33 million Fully static MPC7441: Surface mount 360 ceramic ball grid array (CBGA) 1.5 V 50 mV DC nominal 1.8 V 5% DC or 2.5 V 5% DC
The following list provides a summary of the general parameters of the MPC7441: Technology Transistor count Logic design Packages Core power supply I/O power supply
1.5
1.5.1
Electrical and Thermal Characteristics
DC Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7441.
The tables in this section describe the MPC7441 DC electrical characteristics. Table 2 provides the absolute maximum ratings.
Table 2. Absolute Maximum Ratings1
Characteristic Core supply voltage PLL supply voltage Processor bus supply voltage BVSEL = 0 BVSEL = HRESET or OVDD Input voltage Processor bus JTAG signals Symbol VDD AVDD OVDD OVDD Vin Vin Maximum Value -0.3 to 1.95 -0.3 to 1.95 -0.3 to 1.95 -0.3 to 2.7 -0.3 to OVDD + 0.3 -0.3 to OVDD + 0.3 Unit V V V V V V Notes 4 4 3, 6 3, 7 2, 5
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Electrical and Thermal Characteristics Table 2. Absolute Maximum Ratings1 (continued)
Characteristic Storage temperature range Notes: 1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. Caution: Vin must not exceed OVDD by more than 0.3 V at any time including during power-on reset. Caution: OVDD must not exceed VDD/AVDD by more than 2.0 V at any time including during power-on reset. Caution: VDD/AVDD must not exceed OVDD by more than 0.4 V at any time including during power-on reset. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. BVSEL must be set to 0, such that the bus is in 1.8 V mode. BVSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode. Symbol Tstg Maximum Value -55 to 150 Unit C Notes
2. 3. 4. 5. 6. 7.
Figure 2 shows the undershoot and overshoot voltage on the MPC7441.
OVDD + 20% OVDD + 5% OVDD
VIH
VIL GND GND - 0.3 V GND - 0.7 V Not to Exceed 10% of tSYSCLK
Figure 2. Overshoot/Undershoot Voltage
The MPC7441 provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The MPC7441 core voltage must always be provided at nominal 1.5 V (see Table 4 for actual recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 3. The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied to the OVDD power pins.
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Electrical and Thermal Characteristics Table 3. Input Threshold Voltage Setting
BVSEL Signal 0 HRESET HRESET 1 Processor Bus Input Threshold is Relative to: 1.8 V Not Available 2.5 V 2.5 V Notes 1, 4 1, 3 1, 2 1
Notes: 1. Caution: The input threshold selection must agree with the OVDD/GVDD voltages supplied. See notes in Table 2. 2. To select the 2.5-V threshold option for the processor bus, BVSEL should be tied to HRESET so that the two signals change state together. This is the preferred method for selecting this mode of operation. 3. HRESET is the inverse of HRESET. 4. If used, pulldown resistors should be less than 250 .
Table 4 provides the recommended operating conditions for the MPC7441.
Table 4. Recommended1 Operating Conditions
Recommended Value Characteristic Symbol Min Core supply voltage PLL supply voltage Processor bus supply voltage BVSEL = 0 BVSEL = HRESET or OVDD Input voltage Processor bus JTAG signals Die-junction temperature VDD AVDD OVDD OVDD Vin Vin Tj Max V V V V V V C 2 Unit Notes
1.5 V 50 mV 1.5 V 50 mV 1.8 V 5% 2.5 V 5% GND GND 0 OVDD OVDD 105
Notes: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2. This voltage is the input to the filter discussed in Section 1.9.2, "PLL Power Supply Filtering" and not necessarily the voltage at the AVDD pin which may be reduced from VDD by the filter.
Table 5 provides the package thermal characteristics for the MPC7441.
Table 5. Package Thermal Characteristics
Characteristic CBGA package thermal resistance, junction-to-case thermal resistance (typical) CBGA package thermal resistance, die junction-to-lead thermal resistance (typical) Symbol JC JB Value <0.1 2.2 Rating C/W C/W
Note: Refer to Section 1.9, "System Design Information," for more details about thermal management.
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Electrical and Thermal Characteristics
Table 6 provides the DC electrical characteristics for the MPC7441.
Table 6. DC Electrical Specifications
At recommended operating conditions. See Table 4.
Characteristic
Nominal Bus Voltage1 1.8 2.5 1.8 2.5 -- -- -- -- 1.8 2.5
Symbol
Min OVDD x 0.65 1.7 -0.3 -0.3 1.4 -0.3 -- -- OVDD - 0.45 1.7 -- -- --
Max
Unit
Notes
Input high voltage (all inputs except SYSCLK) Input low voltage (all inputs except SYSCLK) SYSCLK input high voltage SYSCLK input low voltage Input leakage current, Vin = OVDD + 0.3 V High impedance (off-state) leakage current, Vin = OVDD + 0.3 V Output high voltage, IOH = -5 mA
VIH VIH VIL VIL CVIH CVIL Iin ITSI VOH VOH VOL VOL Cin
OVDD + 0.3 OVDD + 0.3 OVDD x 0.35 0.7 OVDD + 0.3 0.4 10 10 -- -- 0.45 0.7 8.0
V V V V V V A A V V V V pF 4 2, 3 2, 3, 5
Output low voltage, IOL = 5 mA
1.8 2.5
Capacitance, Vin = 0 V, f = 1 MHz
All inputs
--
Notes: 1. Nominal voltages; see Table 4 for recommended operating conditions. 2. For processor bus signals, the reference is OVDD. 3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals. 4. Capacitance is periodically sampled rather than 100% tested. 5. The leakage is measured for nominal OVDD and VDD, or both OVDD and VDD must vary in the same direction (for example, both OVDD and VDD vary by either +5% or -5%).
Table 7 provides the power consumption for the MPC7441.
Table 7. Power Consumption for MPC7441
Processor (CPU) Frequency Unit 600 MHz Full-Power Mode Typical Maximum Doze Mode Typical -- -- W 1, 3, 4 11.5 15.4 13.4 17.6 W W 1, 3 1, 2 700 MHz Notes
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Electrical and Thermal Characteristics Table 7. Power Consumption for MPC7441 (continued)
Processor (CPU) Frequency Unit 600 MHz Nap Mode Typical Sleep Mode Typical 0.7 Deep Sleep Mode (PLL Disabled) Typical 410 480 mW 1, 3 0.8 W 1, 3 1.3 1.6 W 1, 3 700 MHz Notes
Notes: 1. These values apply for all valid processor bus ratios. The values do not include I/O supply power (OVDD) or PLL supply power (AVDD). OVDD power is system dependent, but is typically <20% of VDD power. Worst case power consumption for AVDD < 3 mW. 2. Maximum power is measured at nominal VDD (see Table 4) while running an entirely cache-resident, contrived sequence of instructions which keep the execution units, with or without AltiVec, maximally busy. 3. Typical power is an average value measured at the nominal recommended VDD (see Table 4) in a system while running a typical code sequence. 4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep mode. As a result, power consumption for this mode is not tested.
1.5.2
AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC7441. After fabrication, functional parts are sorted by maximum processor core frequency as shown in Section 1.5.2.1, "Clock AC Specifications," and tested for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_EXT and PLL_CFG[0:3] signals. Parts are sold by maximum processor core frequency; see Section 1.11, "Ordering Information."
1.5.2.1
Clock AC Specifications
Table 8. Clock AC Timing Specifications
Table 8 provides the clock AC timing specifications as defined in Figure 3.
At recommended operating conditions. See Table 4.
Maximum Processor Core Frequency Characteristic Symbol 600 MHz Min Processor frequency VCO frequency SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time fcore fVCO fSYSCLK tSYSCLK tKR and tKF 500 1000 33 7.5 -- Max 600 1200 133 30 1.0 700 MHz Min 500 1000 33 7.5 -- Max 700 1400 133 30 1.0 MHz MHz MHz ns ns 2 1 1 1 Unit Notes
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Electrical and Thermal Characteristics Table 8. Clock AC Timing Specifications (continued)
At recommended operating conditions. See Table 4.
Maximum Processor Core Frequency Characteristic Symbol 600 MHz Min SYSCLK duty cycle measured at OVDD/2 SYSCLK jitter Internal PLL relock time tKHKL/tSYSCLK 40 -- -- Max 60 150 100 700 MHz Min 40 -- -- Max 60 150 100 % ps s 3 4, 6 5 Unit Notes
Notes: 1. Caution: The SYSCLK frequency, PLL_EXT and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_EXT, PLL_CFG[0:3] signal description in Section 1.9.1, "PLL Configuration," for valid PLL_EXT and PLL_CFG[0:3] settings. 2. Rise and fall times for the SYSCLK input measured from 0.4 V to 1.4 V. 3. Timing is guaranteed by design and characterization. 4. This represents total input jitter--short term and long term combined--and is guaranteed by design. 5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence. 6. The SYSCLK driver's closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow cascade connected PLL-based devices to track SYSCLK drivers with the specified jitter.
Figure 3 provides the SYSCLK input timing diagram.
SYSCLK VM tKHKL tSYSCLK VM = Midpoint Voltage (OVDD/2) VM VM CVIH CVIL tKR tKF
Figure 3. SYSCLK Input Timing Diagram
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Electrical and Thermal Characteristics
1.5.2.2
Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7441 as defined in Figure 4 and Figure 5.
Table 9. Processor Bus AC Timing Specifications
At recommended operating conditions. See Table 4.
All Speed Grades Parameter Symbol2 Min Mode select input setup to HRESET HRESET to mode select input hold Input setup times: A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], WT, CI, D[0:63], DP[0:7] AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], HRESET, INT, MCP, QACK, SMI, SRESET, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1] Input hold times: A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], WT, CI, D[0:63], DP[0:7] AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], HRESET, INT, MCP, QACK, SMI, SRESET, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1] Output valid times: A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], WT, CI TS D[0:63], DP[0:7] ARTRY/SHD0/SHD1 BR, CKSTP_OUT, DRDY, HIT, PMON_OUT, QREQ] Output hold times: A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], WT, CI TS D[0:63], DP[0:7] ARTRY/SHD0/SHD1 BR, CKSTP_OUT, DRDY, HIT, PMON_OUT, QREQ SYSCLK to output enable SYSCLK to output high impedance (all except TS, ARTRY, SHD0, SHD1) SYSCLK to TS high impedance after precharge Maximum delay to ARTRY/SHD0/SHD1 precharge tMVRH tMXRH tAVKH tIVKH 8 0 2.0 2.0 Max -- -- -- -- tsysclk ns ns 3, 4, 5, 6 3, 5 Unit Notes
ns tAXKH tIXKH 0 0 -- --
ns tKHAV tKHTSV tKHDV tKHARV tKHOV tKHAX tKHTSX tKHDX tKHARX tKHOX tKHOE tKHOZ tKHTSPZ tKHARP -- -- -- -- -- 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- 2.5 2.5 2.5 2.5 2.5 ns -- -- -- -- -- -- 3.5 1 1 ns ns tsysclk tsysclk 5, 7, 10 5, 8, 9, 10
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Electrical and Thermal Characteristics Table 9. Processor Bus AC Timing Specifications (continued)
At recommended operating conditions. See Table 4.
All Speed Grades Parameter Symbol2 Min SYSCLK to ARTRY/SHD0/SHD1 high impedance after precharge tKHARPZ -- Max 2 tsysclk 5, 8, 9, 10 Unit Notes
Notes: 1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal in question. All output timings assume a purely resistive 50- load (see Figure 4). Input and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of the reference and its state for inputs) and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX). 3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 5). 4. This specification is for configuration mode select only. 5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question. 6. Mode select signals are: BVSEL, PLL_CFG[0:3], PLL_EXT, BMODE[0:1]. 7. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then precharged high before returning to high impedance as shown in Figure 6. The nominal precharge width for TS is 0.5 x tSYSCLK, i.e., less than the minimum tSYSCLK period, to ensure that another master asserting TS on the following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge.The high impedance behavior is guaranteed by design. 8. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it low in the first clock following AACK will then go to high impedance for one clock before precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tsysclk; that is, it should be high impedance as shown in Figure 6 before the first opportunity for another master to assert ARTRY. Output valid and output hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design. 9. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of TS. Timing is the same as ARTRY, i.e., the signal is high impedance for a fraction of a cycle, then negated for up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1 is 1.0 tsysclk. The edges of the precharge vary depending on the programmed ratio of core to bus (PLL configurations). 10. Guaranteed by design and not tested.
Figure 4 provides the AC test load for the MPC7441.
Output Z0 = 50 OVDD/2
RL = 50
Figure 4. AC Test Load
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Electrical and Thermal Characteristics
Figure 5 provides the mode select input timing diagram for the MPC7441.
HRESET tMVRH tMXRH Mode Signals VM = Midpoint Voltage (OVDD/2) VM
Figure 5. Mode Input Timing Diagram
Figure 6 provides the input/output timing diagram for the MPC7441.
SYSCLK VM tAVKH tIVKH All Inputs tKHAV tKHDV tKHOV tKHAX tKHDX tKHOX VM tAXKH tIXKH VM
All Outputs (Except TS, ARTRY, SHD0, SHD1)
tKHOE
All Outputs (Except TS, ARTRY, SHD0, SHD1)
tKHOZ
tKHTSPZ tKHTSV tKHTSX tKHTSV TS tKHARPZ tKHARV ARTRY, SHD0, SHD1 tKHARP tKHARX
VM = Midpoint Voltage (OVDD/2)
Figure 6. Input/Output Timing Diagram
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Electrical and Thermal Characteristics
1.5.2.3
IEEE 1149.1 AC Timing Specifications
Table 10 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 8, Figure 9, Figure 10, and Figure 11.
Table 10. JTAG AC Timing Specifications (Independent of SYSCLK)1
At recommended operating conditions. See Table 4.
Parameter TCK frequency of operation TCK cycle time TCK clock pulse width measured at 1.4 V TCK rise and fall times TRST assert time Input setup times: Boundary-scan data TMS, TDI Input hold times: Boundary-scan data TMS, TDI Valid times: Boundary-scan data TDO Output hold times: Boundary-scan data TDO TCK to output high impedance: Boundary-scan data TDO
Symbol fTCLK t TCLK tJHJL tJR and tJF tTRST tDVJH tIVJH tDXJH tIXJH tJLDV tJLOV tJLDX tJLOX tJLDZ tJLOZ
Min 0 30 15 0 25 4 0 20 25 4 4 TBD TBD 3 3
Max 33.3 -- -- 2 -- -- --
Unit MHz ns ns ns ns ns
Notes
2 3
ns -- -- ns 20 25 ns TBD TBD ns 19 9 4, 5 5 4 4 3
Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50- load (see Figure 7). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 3. Non-JTAG signal input timing with respect to TCK. 4. Non-JTAG signal output timing with respect to TCK. 5. Guaranteed by design and characterization.
Figure 7 provides the AC test load for TDO and the boundary-scan outputs of the MPC7441.
Output Z0 = 50 OVDD/2
RL = 50
Figure 7. Alternate AC Test Load for the JTAG Interface
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Electrical and Thermal Characteristics
Figure 8 provides the JTAG clock input timing diagram.
TCLK VM tJHJL tTCLK VM = Midpoint Voltage (OVDD/2) VM VM tJR tJF
Figure 8. JTAG Clock Input Timing Diagram
Figure 9 provides the TRST timing diagram.
TRST VM tTRST VM = Midpoint Voltage (OVDD/2) VM
Figure 9. TRST Timing Diagram
Figure 10 provides the boundary-scan timing diagram.
TCK VM tDVJH Boundary Data Inputs tJLDV tJLDX Boundary Data Outputs tJLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid
Input Data Valid
VM
tDXJH
Figure 10. Boundary-Scan Timing Diagram
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Electrical and Thermal Characteristics
Figure 11 provides the test access port timing diagram.
TCK VM tIVJH TDI, TMS tJLOV tJLOX TDO Output Data Valid Input Data Valid VM
tIXJH
tJLOZ TDO Output Data Valid VM = Midpoint Voltage (OVDD/2)
Figure 11. Test Access Port Timing Diagram
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Pin Assignments
1.6
Part A
Pin Assignments
Figure 12 (in Part A) shows the pinout of the MPC7441, 360 CBGA package as viewed from the top surface. Part B shows the side profile of the CBGA package to indicate the direction of the top surface view.
1 A B C D E F G H J K L M N P R T U V W
Not to Scale
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
Part B
Substrate Assembly Encapsulant View Die
Figure 12. Pinout of the MPC7441, 360 CBGA Package as Viewed from the Top Surface
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Pinout Listings for the 360 CBGA Package
1.7
Pinout Listings for the 360 CBGA Package
NOTE This pinout is not compatible with the MPC750, MPC755, MPC7400, or MPC7410 360 BGA package.
Table 11. Pinout Listing for the MPC7441, 360 CBGA Package
Table 11 provides the pinout listing for the MPC7441, 360 CBGA package.
Signal Name A[0:35]
Pin Number E11, H1, C11, G3, F10, L2, D11, D1, C10, G2, D12, L3, G4, T2, F4, V1, J4, R2, K5, W2, J2, K4, N4, J3, M5, P5, N3, T1, V2, U1, N5, W1, B12, C4, G10, B11 R1 C1, E3, H6, F5, G7 N2 A8 M1 G9 F8 D2 B7 J1 A3 B1 H2 R15, W15, T14, V16, W16, T15, U15, P14, V13, W13, T13, P13, U14, W14, R12, T12, W12, V12, N11, N10, R11, U11, W11, T11, R10, N9, P10, U10, R9, W10, U9, V9, W5, U6, T5, U5, W7, R6, P7, V6, P17, R19, V18, R18, V19, T19, U19, W19, U18, W17, W18, T16, T18, T17, W3, V17, U4, U8, U7, R7, P6, R8, W8, T8 M2 T3, W4, T4, W9, M6, V3, N8, W6 R3 G1, K1, P1, N1 A11 E2
Active High
I/O I/O
I/F Select1 BVSEL
Notes 11
AACK AP[0:4] ARTRY AVDD BG BMODE0 BMODE1 BR BVSEL CI CKSTP_IN CKSTP_OUT CLK_OUT D[0:63]
Low High Low -- Low Low Low Low High Low Low Low High High
Input I/O I/O Input Input Input Input Output Input Output Input Output Output I/O
BVSEL BVSEL BVSEL N/A BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL 1, 7 8 5 6 8
DBG DP[0:7] DRDY DTI[0:3] EXT_QUAL GBL
Low High Low High High Low
Input I/O Output Input Input I/O
BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL 4 4, 13 9
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Pinout Listings for the 360 CBGA Package Table 11. Pinout Listing for the MPC7441, 360 CBGA Package (continued)
Signal Name GND Pin Number B5, C3, D6, D13, E17, F3, G17, H4, H7, H9, H11, H13, J6, J8, J10, J12, K7, K3, K9, K11, K13, L6, L8, L10, L12, M4, M7, M9, M11, M13, N7, P3, P9, P12, R5, R14, R17, T7, T10, U3, U13, U17, V5, V8, V11, V15 B2 D8 D4 G8 B3 A6, A13, A14, A15, A16, A17, A18, A19, B13, B14, B15, B16, B17, B18, B19, C13, C14, C15, C16, C17, C18, C19, D14, D15, D16, D17, D18, D19, E12, E13, E14, E15, E16, E19, F12, F13, F14, F15, F16, F17, F18, F19, G11, G12, G13, G14, G15, G16, G19, H14, H15, H16, H17, H18, H19, J14, J15, J16, J17, J18, J19, K15, K16, K17, K18, K19, L14, L15, L16, L17, L18, L19, M14, M15, M16, M17, M18, M19, N12, N13, N14, N15, N16, N17, N18, N19, P15, P16, P18, P19 E8 C9 B4, C2, C12, D5, E18, F2, G18, H3, J5, K2, L5, M3, N6, P2, P8, P11, R4, R13, R16, T6, T9, U2, U12, U16, V4, V7, V10, V14 B8, C8, C7, D7 A7 D9 A9 G5 P4 E4, H5 F9 A2 A10 K6 E1 F11 C6 Active -- I/O -- I/F Select1 N/A Notes
HIT HRESET INT L1_TSTCLK L2_TSTCLK No Connect
Low Low Low High High --
Output Input Input Input Input --
BVSEL BVSEL BVSEL BVSEL BVSEL --
4
9 12 3
LSSD_MODE MCP OVDD
Low Low --
Input Input --
BVSEL BVSEL N/A
2, 7
PLL_CFG[0:3] PLL_EXT PMON_IN PMON_OUT QACK QREQ SHD[0:1] SMI SRESET SYSCLK TA TBEN TBST TCK
High High Low Low Low Low Low Low Low -- Low High Low High
Input Input Input Output Input Output I/O Input Input Input Input Input Output Input
BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL 8 10
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Pinout Listings for the 360 CBGA Package Table 11. Pinout Listing for the MPC7441, 360 CBGA Package (continued)
Signal Name TDI TDO TEA TEST[0:3] TEST[4] TMS TRST TS TSIZ[0:2] TT[0:4] WT VDD B9 A4 L1 A12, B6, B10, E10 D10 F1 A5 L4 G6, F7, E7 E5, E6, F6, E9, C5 D3 H8, H10, H12, J7, J9, J11, J13, K8, K10, K12, K14, L7, L9, L11, L13, M8, M10, M12 Pin Number Active High High Low -- -- High Low Low High High Low -- I/O Input Output Input Input Input Input Input I/O Output I/O Output -- I/F Select1 BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL N/A 8 2 9 7 7, 14 8 Notes 7
Notes: 1. OVDD supplies power to the processor bus, JTAG, and all control signals; and VDD supplies power to the processor core and the PLL (after filtering to become AVDD). To program the I/O voltage, connect BVSEL to either GND (selects 1.8 V) or to HRESET (selects 2.5 V). If used, the pulldown resistor should be less than 250 . For actual recommended value of Vin or supply voltages see Table 4. 2. These input signals are for factory use only and must be pulled up to OVDD for normal machine operation. 3. These signals are for factory use only and must be left unconnected for normal machine operation. 4. Ignored in 60x bus mode. 5. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going high. 6. This signal must be negated during reset, by pull-up to OVDD or negation by HRESET (inverse of HRESET), to ensure proper operation. 7. Internal pull-up on die. 8. These pins require weak pull-up resistors (for example, 4.7 k) to maintain the control signals in the negated state after they have been actively negated and released by the MPC7441 and other bus masters. 9. These input signals are for factory use only and must be pulled down to GND for normal machine operation. 10. This pin can externally enable the performance monitor counters (PMC) if they are internally enabled by the software. If it will not be used to control the PMC, it should be pulled down to GND so that the software can enable the PMC. 11. Unused address pins must be pulled down to GND. 12. This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance. 13. These signals must be pulled down to GND if unused, or if the MPC7441 is in 60x bus mode. 14. This signal must be asserted during reset, by pull-down to GND or assertion by HRESET, to ensure proper operation.
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Package Description
1.8
1.8.1
Package Description
Package Parameters for the MPC7441, 360 CBGA
Package outline Interconnects Pitch Minimum module height Maximum module height Ball diameter 25 x 25 mm 360 (19 x 19 ball array - 1) 1.27 mm (50 mil) 2.72 mm 3.24 mm 0.89 mm (35 mil)
The following sections provide the package parameters and mechanical dimensions for the CBGA package.
The package parameters are as provided in the following list. The package type is 25 x 25 mm, 360-lead ceramic ball grid array (CBGA).
1.8.2
Mechanical Dimensions for the MPC7441, 360 CBGA
Figure 13 provides the mechanical dimensions and bottom surface nomenclature for the MPC7441, 360 CBGA package.
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Package Description
2X
0.2 D B Capacitor Region
A1 CORNER
D1 0.2 A
A
1
E E2 E1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. TOP SIDE A1 CORNER INDEX IS A METALIZED FEATURE WITH VARIOUS SHAPES. BOTTOM SIDE A1 CORNER IS DESIGNATED WITH A BALL MISSING FROM THE ARRAY.
2X
0.2 C
1 2 3 4 5 6 7 8 9 10 11 1213141516 171819 W V U T R P N M L K J H G F E D C B A
Millimeters DIM A A1 A2 A3
A3 A2 A1 A
MIN 2.72 0.80 1.10 -- 0.82 --
MAX 3.24 1.00 1.34 0.6 0.93 6.15
b D D1 e E E1 E2
25.00 BSC 1.27 BSC 25.00 BSC -- 8.28 10.2 --
e
360X
b
0.3 A B C 0.15 A
Figure 13. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7441, 360 CBGA
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System Design Information
1.9
System Design Information
This section provides system and thermal design recommendations for successful application of the MPC7441.
1.9.1
PLL Configuration
The MPC7441 PLL is configured by the PLL_EXT and PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. PLL_EXT will normally be pulled low but can be asserted for extended modes of operation. The PLL configuration for the MPC7441 is shown in Table 12 for a set of example frequencies. In this example, shaded cells represent settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the 600-MHz column in Table 8.
Table 12. MPC7441 Microprocessor PLL Configuration Example for 600 MHz Parts
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_EXT PLL_CFG [0:3] Bus-toCore-toBus Bus Bus Bus Bus Bus Bus Core VCO 33.3 MHz 50 MHz 66.6 MHz 75 MHz 83 MHz 100 MHz 133 MHz Multiplier Multiplier 0.5x 2x 2.5x 3x 3.5x 4x 4.5x 5x 5.5x 6x 6.5x 7x 7.5x 8x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 16 (33) 66 (133) 83 (166) 100 (200) 116 (233) 133 (266) 150 (300) 166 (333) 183 (366) 200 (400) 216 (433) 233 (466) 250 (500) 266 (533) 25 (50) 100 (200) 125 (250) 150 (300) 175 (350) 200 (400) 225 (450) 250 (500) 275 (550) 300 (600) 325 (630) 350 (700) 375 (750) 400 (800) 33 (66) 133 (266) 166 (333) 200 (400) 233 (466) 266 (533) 300 (600) 333 (666) 366 (733) 400 (800) 433 (866) 466 (933) 500 (1000) 533 (1066) 37 (75) 150 (300) 187 (375) 225 (450) 262 (525) 300 (600) 337 (675) 375 (750) 412 (825) 450 (900) 488 (975) 525 (1050) 563 (1125) 600 (1200) 47 (83) 166 (333) 208 (415) 250 (500) 291 (581) 333 (666) 374 (747) 415 (830) 457 (913) 498 (996) 540 (1080) 581 (1162) 623 (1245) 664 (1328) 50 (100) 200 (400) 250 (500) 300 (600) 350 (700) 400 (800) 450 (900) 500 (1000) 550 (1100) 600 (1200) 650 (1300) 700 (1400) 750 (1500) 66 (133) 266 (533) 333 (666) 400 (800) 466 (933) 533 (1066) 600 (1200) 667 (1333) 733 (1466)
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0000 0100 0110 1000 1110 1010 0111 1011 1001 1101 0101 0010 0001 1100
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System Design Information Table 12. MPC7441 Microprocessor PLL Configuration Example for 600 MHz Parts (continued)
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_EXT PLL_CFG [0:3] Bus-toCore-toBus Bus Bus Bus Bus Bus Bus Core VCO 33.3 MHz 50 MHz 66.6 MHz 75 MHz 83 MHz 100 MHz 133 MHz Multiplier Multiplier 9x 10x 11x 12x 13x 14x 15x 16x 2x 2x 2x 2x 2x 2x 2x 2x 300 (600) 333 (666) 366 (733) 400 (800 433 (866) 466 (933) 500 (1000) 533 (1066) PLL off, SYSCLK clocks core circuitry directly PLL off, no core clocking occurs 450 (900) 500 (1000) 550 (1100) 600 (1200) 650 (1300) 700 (1400) 750 (1500) 600 (1200) 667 (1333) 733 (1466) 675 (1350) 750 (1500) 747 (1494)
1 1 1 1 1 1 1 1 0 0
0111 1010 1001 1011 0101 1100 0001 1101 0011 1111
PLL off/bypass PLL off
Notes: 1. PLL_CFG[0:3] settings not listed are reserved. 2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the MPC7441; see Section 1.5.2.1, "Clock AC Specifications," for valid SYSCLK, core, and VCO frequencies. 3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled. However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be driven at one-half the frequency of SYSCLK and offset in phase to meet the required input setup tIVKH and hold time tIXKH (see Table 9). The result will be that the processor bus frequency will be one-half SYSCLK while the internal processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 4. In PLL-off mode, no clocking occurs inside the MPC7441 regardless of the SYSCLK input.
1.9.2
PLL Power Supply Filtering
The AVDD power signal is provided on the MPC7441 to provide power to the clock generation PLL. To ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in Figure 14 using surface mount capacitors with minimum effective series inductance (ESL) is recommended. The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby circuits. It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the 360 CBGA footprint and very close to the periphery of the 483 CBGA footprint, without the inductance of vias.
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System Design Information
10 VDD 2.2 F 2.2 F Low ESL Surface Mount Capacitors GND AVDD
Figure 14. PLL Power Supply Filter Circuit
1.9.3
Power Supply Voltage Sequencing
The notes in Table 2 contain cautions about the sequencing of the external bus voltages and core voltage of the MPC7441 (when they are different). These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection diodes will be forward-biased and excessive current can flow through these diodes. If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 15 can be added to meet these requirements. The 30BF10 diodes (see Figure 15) control the maximum potential difference between the external bus and core power supplies on power-up and the 1N5820 diodes regulate the maximum potential difference on power-down.
2.5 V 30BF10 30BF10 1.5 V
1N5820
1N5820
Figure 15. Example Voltage Sequencing Circuit
1.9.4
Decoupling Recommendations
Due to the MPC7441 dynamic power management feature, large address and data buses, and high operating frequencies, the MPC7441 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC7441 system, and the MPC7441 itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD and OVDD pin of the MPC7441. It is also recommended that these decoupling capacitors receive their power from separate VDD, OVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. These capacitors should have a value of 0.01 F or 0.1 F. Only ceramic surface mount technology (SMT) capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along the length of the part. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous recommendations for decoupling Motorola microprocessors, multiple small capacitors of equal value are recommended over using multiple values of capacitance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response time
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MPC7441 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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System Design Information
necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors: 100-330 F (AVX TPS tantalum or Sanyo OSCON).
1.9.5
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OVDD. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, OVDD, and GND pins in the MPC7441.
1.9.6
Output Buffer DC Impedance
The MPC7441 processor bus drivers is characterized over process, voltage, and temperature. To measure Z0, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 16). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the pad equals OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.
OVDD
RN
SW2 Data Pad SW1
RP
OGND
Figure 16. Driver Impedance Measurement
Table 13 summarizes the signal impedance results. The impedance increases with junction temperature and is relatively unaffected by bus voltage.
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MPC7441 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
System Design Information Table 13. Impedance Characteristics
VDD = 1.5 V, OVDD = 1.8 V 5%, Tj = 5-85C
Impedance Z0 Typical Maximum
Processor Bus 33-42 31-51
Unit
1.9.7
Pull-Up/Pull-Down Resistor Requirements
The MPC7441 requires high-resistive (weak: 4.7 k) pull-up resistors on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the MPC7441 or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1. Some pins designated as being for factory test must be pulled up to OVDD or down to GND to ensure proper device operation. For the MPC7441, 360 BGA, the pins that must be pulled up to OVDD are: LSSD_MODE and TEST[0:3]; the pins that must be pulled down to GND are: L1_TSTCLK and TEST[4]. In addition, the MPC7441 has one open-drain style output that requires a pull-up resistor (weak or stronger: 4.7 k-1 k) if it is used by the system. This pin is CKSTP_OUT. If a pull-down resistor is used to configure BVSEL, the resistor should be less than 250 (see Table 11). During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. Because the MPC7441 must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the MPC7441 or by other receivers in the system. It is recommended that these signals be pulled up through weak (4.7 k) pull-up resistors by the system, or that they may be otherwise driven by the system during inactive periods of the bus. The snooped address and transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL. If extended addressing is not used, A[0:3] are unused and must be be pulled low to GND through weak pull-down resistors. If the MPC7441 is in 60x bus mode, DTI[0:3] must be pulled low to GND through weak pull-down resistors. The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The data bus signals are: D[0:63] and DP[0:7]. If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left unconnected by the system.
1.9.8
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical.
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MPC7441 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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System Design Information
The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 17 allows the COP to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. An optional pull-down resistor on TRST can be populated to ensure that the JTAG scan chain is initialized during power-on if the JTAG interface and COP header will not be used; otherwise, this resistor should be unpopulated and TRST is asserted when the system reset signal (HRESET) is asserted and the JTAG interface is responsible for driving TRST when needed. The COP header shown in Figure 17 adds many benefits--breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features are possible through this interface--and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. There is no standardized way to number the COP header shown in Figure 17; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 17 is common to all known emulators. The QACK signal shown in Figure 17 is usually connected to the PCI bridge chip in a system and is an input to the MPC7441 informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power mode selection. In order for COP to work, the MPC7441 must see this signal asserted (pulled down). While shown on the COP header, not all emulator products drive this signal. If the product does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator products implement open-drain type outputs and can only drive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is deasserted when it is not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never necessary to populate both in a system. To preserve correct power down operation, QACK should be merged via logic so that it also can be driven by the PCI bridge.
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MPC7441 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
System Design Information
From Target Board Sources (if any)
SRESET HRESET QACK 13 11 HRESET SRESET 10 k 10 k
SRESET HRESET
OVDD OVDD OVDD 10 k OVDD 10 k 2 k3 10 k TRST GND OVDD OVDD
1 3 5 7 9 11
2 4 6 8 10 12
4 6 5
1
TRST VDD_SENSE 2 k
15 Key 14 COP Header
CHKSTP_OUT 10 k
CHKSTP_OUT 10 k OVDD OVDD CHKSTP_IN TMS
2
KEY 13 No pin
CHKSTP_IN 8 TMS 9 1 3 7 2 10 12 16 QACK NC NC TDO TDI TCK
15
16
COP Connector Physical Pin Out
TDO TDI TCK QACK 2 k4 10 k5 OVDD
Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7450. Connect pin 5 of the COP header to OVDD with a 10 K pull-up resistor. 2. Key location; Pin 14 is not physically present on the COP header. 3. .Component not populated. Populate only if JTAG interface is unused. 4. Component not populated. Populate only if debug tool does not drive QACK. 5. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.
Figure 17. JTAG Interface Connection
1.9.9
Thermal Management Information
This section provides thermal management information for the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design--the heat sink, airflow, and thermal interface material. To reduce the die-junction temperature, heat
MOTOROLA
MPC7441 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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System Design Information
sinks may be attached to the package by several methods--spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly (see Figure 18); however, due to the potential large mass of the heat sink, attachment through the printed circuit board is suggested. If a spring clip is used, the spring force should not exceed 5.5 pounds.
Heat Sink Heat Sink Clip
CBGA Package
Thermal Interface Material
Printed-Circuit Board
Figure 18. Package Exploded Cross-Sectional View with Several Heat Sink Options
The board designer can choose between several types of heat sinks to place on the MPC7441. There are several commercially available heat sinks for the MPC7441 provided by the following vendors: Chip Coolers Inc. 333 Strawberry Field Rd. Warwick, RI 02887-6979 Internet: www.chipcoolers.com International Electronic Research Corporation (IERC) 135 W. Magnolia Blvd. Burbank, CA 91502 Internet: www.ctscorp.com Thermalloy 2021 W. Valley View Lane Dallas, TX 75234-8993 Internet: www.thermalloy.com Wakefield Engineering 100 Cummings Center, Suite 157H Beverly, MA 01915 Internet: www.wakefield.com Aavid Engineering 250 Apache Trail Terrell, TX 75160 Internet: www.aavid.com 800-227-0254 (USA/Canada) 401-739-7600
818-842-7277
972-243-4321
781-406-3000
972-551-7330
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MPC7441 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
System Design Information
Cool Innovations Inc. 260 Spinnaker Way, Unit 8 Concord, Ontario L4K 4P9 Canada Internet: www.coolinnovations.com
905-760-1992
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
1.9.9.1
Internal Package Conduction Resistance
For the exposed-die packaging technology, shown in Table 3, the intrinsic conduction thermal resistance paths are as follows: * * The die junction-to-case (or top-of-die for exposed silicon) thermal resistance The die junction-to-ball thermal resistance
Figure 19 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
External Resistance Radiation Convection
Heat Sink Thermal Interface Material Internal Resistance Die/Package Die Junction Package/Leads
Printed-Circuit Board
Radiation Convection External Resistance (Note the internal versus external package resistance)
Figure 19. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. Because the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. Thus, the thermal interface material and the heat sink conduction/convective thermal resistances are the dominant terms.
1.9.9.2
Thermal Interface Materials
A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 20 shows the thermal performance of three thin-sheet thermal-interface materials (silicone,
MOTOROLA
MPC7441 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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System Design Information
graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately 7 times greater than the thermal grease joint. Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 18). Therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure and is recommended due to the high power dissipation of the MPC7441. Of course, the selection of any thermal interface material depends on many factors--thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc.
2
Silicone Sheet (0.006 inch) Bare Joint Floroether Oil Sheet (0.007 inch) Graphite/Oil Sheet (0.005 inch) Synthetic Grease
Specific Thermal Resistance (Kin2/W)
1.5
1
0.5
0 0 10 20 30 40 50 60 70 80 Contact Pressure (psi)
Figure 20. Thermal Performance of Select Thermal Interface Material
The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. There are several commercially available thermal interfaces and adhesive materials provided by the following vendors: Dow-Corning Corporation Dow-Corning Electronic Materials PO Box 0997 Midland, MI 48686-0997 Internet: www.dow.com Chomerics, Inc. 77 Dragon Court Woburn, MA 01888-4014 Internet: www.chomerics.com 800-248-2481
781-935-4850
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MPC7441 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
System Design Information
Thermagon Inc. 3256 West 25th Street Cleveland, OH 44109-1668 Internet: www.thermagon.com Loctite Corporation 1001 Trout Brook Crossing Rocky Hill, CT 06067-3910 Internet: www.loctite.com
888-246-9050
860-571-5100
The following section provides a heat sink selection example using one of the commercially available heat sinks.
1.9.9.3
Heat Sink Selection Example
Tj = Ta + Tr + (jc + int + sa) x Pd
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: where: Tj is the die-junction temperature Ta is the inlet cabinet ambient temperature Tr is the air temperature rise within the computer cabinet
jc is the junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance
Pd is the power dissipated by the device During operation, the die-junction temperatures (Tj) should be maintained less than the value specified in Table 4. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30 to 40C. The air temperature rise within a cabinet (Tr) may be in the range of 5 to 10C. The thermal resistance of the thermal interface material (int) is typically about 1.5C/W. For example, assuming a Ta of 30C, a Tr of 5C, a CBGA package jc = 0.1, and a typical power consumption (Pd) of 11.5 W, the following expression for Tj is obtained: Die-junction temperature: Tj = 30C + 5C + (0.1C/W + 1.5C/W + sa) x 11.5 W For this example, a sa value of 4.4C/W or less is required to maintain the die junction temperature below the maximum value of Table 4. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature--airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection,
MOTOROLA
MPC7441 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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Document Revision History
and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as system-level designs.
1.10 Document Revision History
Table 14 provides a revision history for this hardware specification.
Table 14. Document Revision History
Document Revision Rev 0 Initial release. Substantive Change(s)
1.11 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in Section 1.11.1, "Part Numbers Fully Addressed by This Document."
1.11.1 Part Numbers Fully Addressed by This Document
Table 15 provides the Motorola part numbering nomenclature for the MPC7441. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Motorola sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision level code which refers to the die mask revision number.
Table 15. Part Numbering Nomenclature
XPC
Product Code XPC2
7441
Part Identifier 7441
RX
Package RX = CBGA
nnn
Processor Frequency1 600 700
x
Application Modifier L: 1.5 V 50 mV 0 to 105C
x
Revision Level G: 2.3; PVR = 8000 0210
Notes: 1. Processor core frequencies supported by parts addressed by this specification only. Parts addressed by Part Number Specifications may support other maximum core frequencies. 2. The X prefix in a Motorola part number designates a "Pilot Production Prototype" as defined by Motorola SOP 3-13. These are from a limited production volume of prototypes manufactured, tested, and Q.A. inspected on a qualified technology to simulate normal production. These parts have only preliminary reliability and characterization data. Before pilot production prototypes may be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur while shipping pilot production prototypes.
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MPC7441 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Ordering Information
1.11.2 Part Marking
Parts are marked as the example shown in Figure 21.
XPC7441 RX600LG MMMMMM ATWLYYWWA
7441 Notes: BGA MMMMMM is the 6-digit mask number. ATWLYYWWA is the traceability code. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
Figure 21. Part Marking for BGA Device
MOTOROLA
MPC7441 RISC Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
39
HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC:
Information in this document is provided solely to enable system and software
Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors DOCUMENT COMMENTS: FAX (512) 933-2625, Attn: RISC Applications Engineering
implementers to use . There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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